Time-interleaved sampling architectures are the mainstream solution for overcoming the performance bottleneck of single-channel analog-to-digital converters (ADCs) and enabling ultra-high-speed data acquisition. However, their performance is severely limited by nonideal channel frequency responses and inter-channel mismatch errors. Existing calibration schemes typically employ finite impulse response (FIR) filters and periodic time-varying filters to compensate for these errors separately. However, serial implementations usually restrict throughput to several hundred mega points per second (Mpts/s), which cannot meet the real-time processing requirements of radar, communication, and other applications that demand several giga-points per second (Gpts/s) throughput. To increase throughput, the most straightforward approach is to adopt a parallel calibration architecture; however, direct parallelization leads to a dramatic increase in hardware resource consumption. To resolve the trade-off between throughput and resource utilization, an efficient calibration architecture is proposed. First, an adaptive weighted least-squares algorithm is introduced to optimize the FIR filter design. By dynamically adjusting frequency-dependent weights, the filter order is reduced while maintaining calibration accuracy. Furthermore, a spectrum-folding structure is proposed to halve the number of parallel inverse fast Fourier transform (IFFT) operations in the periodic time-varying filter, significantly reducing hardware resources. An 8-channel parallel calibration architecture implemented on a field-programmable gate array (FPGA) is validated using a platform with a 20 GSPS sampling rate and 8 GHz bandwidth. The achieved throughput reaches 2 giga points per second (Gpts/s), while the post-calibration accuracy is comparable to that of a serial architecture. Measurement results demonstrate that the amplitude flatness is improved from 4 dB to ±0.25 dB, and the spurious-free dynamic range (SFDR) is enhanced from 25.8 dB to 46.9 dB. The proposed scheme effectively overcomes the bottleneck of high-speed, real-time processing and provides a resource-efficient, high-performance solution for high-speed data acquisition systems.