Aiming at the problems of high delay and high power consumption of the multiplier part in RISC-V processors, this paper proposes an improved multiplier optimisation design based on symbol extension on the basis of the booth2 algorithm, which reduces the execution cycle of multiplication instructions in the processor and supports the operation of signed/unsigned numbers at the same time. The improved CSA32 compressor and the choice to alternate the Wallace tree structure with a 3.2 compressor and a 4.2 compressor improves the compression efficiency of the partial product, and also reduces the critical path delay and improves the speed of the multiplier operation. The coding verification and functional simulation of the multiplier are carried out using verification tools such as NC-verilog, and the comprehensive analysis is carried out using. Design complier at SIMC 180 nm process, and the results show that the multiplier designed in this paper reduces the multiplication instruction execution cycle by 88.2% compared with PicoRV32, the area and power consumption are better than those of the same type of multiplier.