Research on dynamic reconfigurable implementation of context adaptive binary arithmetic coding
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1. School of electrical and control engineering, Xi’an University of Science and Technology, Xi’an 710600, China; 2. School of computer science and technology, Xi’an University of Science and Technology, Xi’an 710600, China; 3. School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’an 710121, China

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TP919.81

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    Abstract:

    In response to the slow coding speed and high resource overhead of the Context-based adaptive binary arithmetic coding under the H.266/VVC video coding standard, the reconfigurable oriented architecture optimized the coding architecture based on the intrinsic parallelism of the algorithm, and designs and implements a parallel mapping method for the CABAC encoder in conventional coding mode based on a dynamically reconfigurable array processor. The array structure is able to dynamically reconfigure the optimized algorithm according to the coding input, and the software reconfiguration method is used to implement the entropy coding process without the high resource overhead of dedicated hardware encoders. Simulation results show that the mapped encoding process completes five binary sequences per encoding cycle with an average encoding efficiency of 384.13Mbin/s. FPGA based test results show that the software reconstruction approach reduces the resource overhead and improves the encoding efficiency by 5.47% compared to dedicated hardware implementations, and improves the encoding efficiency by 7.03% compared to similar reconfigurable video encoding structures.

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  • Received:
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  • Online: March 29,2024
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