Multitemperature and low power test scheduling method for SoC in deep submicron technology
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1.Department of Electrial Information Engineering,Hunan Institute of Traffic Engineering,Hengyang 421001,China; 2. Department of Computer Science,Hengyang Normal University,Hengyang 421002,China

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TP391.7

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    Abstract:

    Systems on Chip implemented with deep submicron,in order to solve due to the temperature uncertainty induced by process variation, proposed a MultiTemperature and Low Power Test Scheduling method. The method adopted to build multiple temperature sensor in the chip, through the temperature sensor to sense the temperature of the builtin, multipoint collection in the core part of SoC, the highest value of using temperature feedback to the control system, temperature regulation and control. The scheduling test satisfies a condition in the temperature, power consumption and bus bandwidth situation, avoid chip local overheating. Experimental results on ITC′02 benchmark circuits show that ,compared with the literature [2], the method can guarantee the chip thermal safety at the same time, the average CPU time decreased by more than 10.33%, the test application time average reduction of 11.14%

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  • Received:
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  • Online: May 27,2016
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