In a high-speed satellite data transmission system, inevitable symbol timing offsets exist between transmitters and receivers, and Doppler effects further amplify these. These issues can beeffectively corrected by clock recovery algorithms. However, existing clock recovery algorithms often suffer from performance degradation due to a large number of parallel processing paths, high implementation complexity, making it difficult to meet the requirements of higher symbol rate and greater timing offset tolerance in resource-constrained systems. Thus, this paper proposes an optimized parallel implementation architecture based on traditional feedforward clock recovery structure. By redesigning the architectures of the timing controller, interpolation filter, and symbol extraction module, the proposed structure enables efficient symbol timing recovery with two samples per symbol. Simultaneously, the LEE timing error detector is enhanced to improve timing error estimation accuracy and timing frequency offset tolerance. Simulation and FPGA board-level tests demonstrate that the proposed architecture can tolerate timing frequency offset up to ±1 000×10-6 under QPSK modulation, and has a stable bit error rate in long-term tests. Furthermore, when implementing a real-time receiver system with 2.5 GBaud symbol rate, the proposed parallel structure saves about 36% of the LUT resources, more than 45% of the Register and about 20% of the DSP resources, showing significant value in resource-constrained high-speed real-time communication systems.