In the broadband signal sampling system, the sampler is an important component. It adopts a symmetrical structure internally to reduce common-mode interference during sampling. It achieves transient sampling and holding of broadband signals by triggering the internal fast recovery diode to conduct rapidly with a narrow pulse signal. However, inconsistent characteristics of the internal diodes and the width of the external narrowband trigger signal being too wide can both lead to poor symmetry of the two output signals and inaccurate sampling. To address these issues, an offset adjustment circuit based on FPGA was designed to compensate for the offset of the sampler′s output signals. After offset compensation, the amplitude error of the two output signals is approximately 3 mV, meeting the symmetry requirements. A narrow pulse trigger circuit was designed using step fast recovery diodes. The trigger signal generated by the trigger circuit has a falling edge time of about 50 ps and an amplitude of 17 V. The measured results show that this signal can trigger the sampler to achieve sampling of signals up to 30 GHz.