The Hough Transform is a commonly used method for detecting lines and has excellent interference resistance and robustness. However, due to its high computational complexity and large storage requirements, deploying the Hough Transform on hardware is challenging. This study proposes an improved Hough Transform algorithm based on the concept of hierarchical Hough Transform. The algorithm decomposes a single Hough Transform into two transformation operations. The first operation involves downsampling the image, which reduces the storage demand of the first-level voting unit. The storage range of the second operation′s voting unit is limited by the parameters obtained from the first operation, effectively addressing the issue of high storage requirements for hardware deployment. Moreover, by improving the Hough Transform algorithm using trigonometric transformation formulas, each transformation can be designed with parallel pipelining, enhancing computational efficiency. A hierarchical pipelined Hough Transform hardware architecture based on FPGA has been implemented. Experimental results show that the proposed architecture reduces on-chip RAM resource usage by 89.8% compared to the classic Hough Transform hardware architecture, and the detection accuracy is improved by 39.94%. At a clock frequency of 100 MHz, it takes 13.11 ms to detect lines in a 1 024×1 024 image, which is a significant improvement over the speed of software-based Hough Transform line detection.