This study presents a design of a non-zero speed start-stop and low-power stepper motor controller. To achieve such design, the acceleration-deceleration curve algorithm for the realization of non-zero speed start-stop, and the hardware-logic design for the realization of low-power dissipation, have been proposed to improve the performance of the stepper motor open-loop control method. The acceleration-deceleration curve algorithm is able to divide the stepper motor rotation process to 4 different modes so that to establish any desired linear motor velocity profile, to tackle the problem of achieving the performance of non-zero speed start-stop. In this paper, the control pulse periods of the 4 different linear acceleration-deceleration process are theoretically derived; Then the hardware-logic model of the acceleration-deceleration process is optimized with the assistane of the Pipeline Design concept. The IP core of the stepper motor controller is built on a Field Programmable Gate Array (FPGA) , and ultilize the low-power ICs (e.g., Clock-Gating Technique) to achieve the low-power performance of the controller. Finally, an experimental platform is setup to demonstrate that, the IP core on FPGA is capable for the non-zero speed start-stop with 4 modes, and is able to drive the motor timely and precisely. The empirical results with statistical analysis show the proposed design is feasible and efficient, and successfully achieve 20% better control performance, 30% less electronic system circuit area, and 53% less power dissipation.