On the basis of Dynamic Partial Reconfiguration (DPR) method Early Access Partial Reconfiguration (EAPR), design method of selfreconfiguration embedded system implemented on FPGA is studied. The hardware platform of the embedded system containing a custommade IP is built by integrating merchant IPs resorting to the development tool ISE12.4 provided by Xilinx. Twodimension reconfiguration technology is used in the design of the system which includes three Reconfigurable Partitions (RPs) and four Reconfigurable Modules (RMs) are available to each RP. Afterward, it is implemented on Virtex5 FPGA to verify the feasibility of the method. Via this method, the development complexity is reduced while development flexibility is improved, achieving lower cost, less time to market and power consumption reduction.