基于FPGA的IRIG-B码产生器设计与实现
DOI:
CSTR:
作者:
作者单位:

作者简介:

通讯作者:

中图分类号:

基金项目:


Design and implication of IRIG-B code generator based on FPGA
Author:
Affiliation:

Fund Project:

  • 摘要
  • |
  • 图/表
  • |
  • 访问统计
  • |
  • 参考文献
  • |
  • 相似文献
  • |
  • 引证文献
  • |
  • 资源附件
  • |
  • 文章评论
    摘要:

    随着大规模集成电路和可编程技术的发展,对靶场时统设备的可编程度、集成度的要求越来越高,特别是对于车载测控设备,由于受空间、运输等条件的限制,对时统设备的体积、可靠性提出了更高的要求。结合靶场时统研究项目,提出了一种基于FPGA的IRIGB码产生器的设计方案,以CycloneⅣ FPGA芯片EP4CE22为核心,采用原理图和Verilog语言进行编程实现。它具有操作简单、可靠性高、功能拓展性强、体积小等优点,可广泛应用于靶场测控设备之中。

    Abstract:

    With the development of large-scale integrated circuit and programmable technique, the degree of integration and programmable ability for timing equipment have been required higher and higher in the test range. As the restriction of space and transportation condition, it puts forward higher requirements for the volume and reliability of timing equipment especially for the vehicle equipment. Combining with the research project of test range timing equipment, a design project of IRIGB code generator is proposed based on FPGA by the CycloneⅣ FPGA chip EP4CE22 as the core and schematic diagram and Verilog language programming. The system has the characters of simple operation, high reliability, smaller volume and strong function expansion, which can widely be applied to measurement and control equipment of test range.

    参考文献
    相似文献
    引证文献
引用本文

冯胜民,陈娟花,王国林,陈思兵.基于FPGA的IRIG-B码产生器设计与实现[J].电子测量技术,2015,38(5):67-71

复制
分享
文章指标
  • 点击次数:
  • 下载次数:
  • HTML阅读次数:
  • 引用次数:
历史
  • 收稿日期:
  • 最后修改日期:
  • 录用日期:
  • 在线发布日期: 2015-06-05
  • 出版日期:
文章二维码
×
《电子测量技术》
财务封账不开票通知